Technical Field
The present invention relates to a package substrate for a multichip package; especially relates to a package substrate having lateral communication circuitry for signal communication between chips within the multichip package.
Description of Related Art
FIG. 1 Shows a Prior Art.
FIG. 1 shows a prior art U.S. Pat. No. 8,901,748. It disclosed a semiconductor package 10 which has an embedded interconnect bridge element 28 with circuitry 34 and metal pad 35 for signal communication between chips 14, 16 configured on top of the package substrate 12. The package 10 is formed on a package substrate 12 that carries the semiconductor dies 14, 16. A cover 18 covers the substrate and the two dies 14, 16. A cooling fin 22 is attached to the top surface of the cover 18. The embedded interconnect bridge element 28 provides circuitry 34 and metal pad 35 for communication between the CPU 16 and memory 14 within the package. The two dies 14 and 16 are coupled through solder balls 24 and metal vias 26 to a power source (not shown) outside the package. The interconnect bridge element 28 provides connectors 30 to the CPU die 16 and provides connectors 32 to the memory 14. The CPU 16 has a first interconnect area 40 closest to the memory 14 for connecting through the embedded bridge element 28 to the memory 14. The CPU 16 has a second interconnect area 42 for connecting with metal vias 26 for power and external data input and output.
The embedded interconnect bridge element 28 disclosed in the prior art needs to be prepared in a separate fabrication process and then embedded in the package substrate, several considerations such as fabrication, singulation, registration and coefficient of thermal expansion (CTE) problem . . . etc., need to be taken care. A simpler structure and fabricating process with higher circuitry density and higher reliability for a multichip package need to be developed.